An Architecture-Oriented Approach to Code Compression for Embedded Processors

This paper presents an efficient and general framework for code compression for embedded systems. The method is based on simple Huffman encoding, but where limited yet powerful higher-order correlations are captured and exploited by using architecture-oriented models. The proposed symbol formation, modeling and encoding steps together achieve high-quality code compression, yet the decoding procedure is straightforward, and can be implemented by a simple decoder. To avoid modifications of microprocessor cores, the decoder is placed between the instruction memory and cache, and is triggered only on cache refills. Applying our framework to ARM benchmark programs, including from MediaBench, the best code compression ratio achieved is 48.1%, and the best overall ratio achieved is 56.7% (including decoder hardware overheads). The average overall ratio is 59.4%. We believe this work is the first to exploit a wide range of detailed architectural information, under a higher-order statistical model, in an effective and practical code compression scheme for embedded systems.